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AT91EB55 Evaluation Board
.............................................................................
User Guide
Table of Contents
Section 1 Overview............................................................................................... 1-1
1.1 1.2 1.3 Scope........................................................................................................1-1 Deliverables ..............................................................................................1-1 The AT91EB55 Evaluation Board .............................................................1-1
Section 2 Setting Up the AT91EB55 Evaluation Board ........................................ 2-1
2.1 2.2 2.3 2.4 2.5 2.6 2.7 Electrostatic Warning ................................................................................2-1 Requirements............................................................................................2-1 Layout .......................................................................................................2-1 Jumper Settings ........................................................................................2-3 Powering Up the Board.............................................................................2-3 Measuring Current Consumption on the AT91M55800A ..........................2-3 Testing the AT91EB55 Evaluation Board .................................................2-4
Section 3 The On-board Software ........................................................................ 3-1
3.1 3.2 3.3 3.4 3.5 AT91EB55 Evaluation Board ....................................................................3-1 The Boot Software Program .....................................................................3-1 Programmed Default Memory Mapping ....................................................3-2 The SRAM Downloader ............................................................................3-2 The Angel Debug Monitor .........................................................................3-2
Section 4 Circuit Description................................................................................. 4-1
4.1 4.2 AT91M55800A Processor .........................................................................4-1 Expansion Connectors and JTAG Interface..............................................4-1 I/O Expansion Connector ...................................................................4-1 EBI Expansion Connector ..................................................................4-1 JTAG Interface ...................................................................................4-2
4.2.1 4.2.2 4.2.3 4.3 4.4 4.5 4.6 4.7
Memories ..................................................................................................4-2 ADC and DAC Peripheral Connections ....................................................4-2 Power and Crystal Quartz .........................................................................4-2 Push Buttons, LEDs, Reset and Serial Interface ......................................4-3 Layout Drawing .........................................................................................4-3
iii
Table of Contents
Section 5 Appendix A - Configuration Straps....................................................... 5-1
5.1 5.2 5.3 5.4 Configuration Straps (CB1 - 15, JP1 - 9).................................................5-1 Power Consumption Measurement Straps (JP5, JP9) .............................5-4 Ground Links (JP6) ...................................................................................5-4 Increasing Memory Size ...........................................................................5-5
Section 6 Appendix B - Schematics..................................................................... 6-1
6.1 Schematics ...............................................................................................6-1
Section 7 Appendix C - Bill of Material ................................................................ 7-1 Section 8 Appendix D - Flash Memory ................................................................ 8-1
iv
Section 1 Overview
1.1
Scope
The AT91EB55 Evaluation Board enables real-time code development and evaluation. It supports the AT91M55800A. This user guide focuses on the AT91 Evaluation Board as an evaluation and demonstration platform: Section 1 provides an overview.
Appendixes A and B cover configuration straps and schematics including pin connectors.
1.2
Deliverables
1.3
The AT91EB55 The board consists of an AT91M55800A, together with several peripherals: Two serial ports Evaluation Board
AT91EB55 Evaluation Board User Guide

Section 2 describes how to setup the evaluation board. Section 3 describes the on-board software. Section 4 contains a description of the circuit board.
The evaluation board is supplied with a DB9 plug to DB9 socket straight through serial cable to connect the target evaluation board to a PC. There is also a bare power lead with a 2.1 mm jack on one end for connection to a bench power supply. The evaluation board is also delivered with a CD-ROM that contains an evaluation version of Software Development Toolkit and the documentation that outlines the AT91 microcontroller family. The evaluation board is capable of supporting different kinds of debugging systems using an ICE interface or the on-board AngelTM Debug Monitor. Refer to the EB55 "Getting Started" tutorial documents for recommendations on using the evaluation board in a full debugging environment.
Reset push button An indicator which memorizes a reset appearance Memory clear for the reset indicator Four user-defined push buttons Eight LEDs 256K byte of 16-bit SRAM (upgradable to 1 MB) 2M bytes of 16-bit Flash (of which 1 MB is available for user software) 4M bytes of Serial Data Flash (upgradeable to 16 MB)
1-1
Overview 64K bytes of E2PROM with I2C access 32K bytes of SPI E2PROM 2 x 32 pin EBI expansion connector 3 x 32 pin I/O expansion connector 20-pin JTAG interface connector
If required, user-defined peripherals can also be added to the board. See "Appendix A" for details. Figure 1-1. AT91EB55 Block Diagram
AT91M55800 8K byte RAM ARM7TDMI Processor JTAG-ICE Connector ASB SRAM Flash EBI Expansion Connector
Reset Controller
16 MHz XTAL
Push Buttons
Reset Controller
Wake Up Push Button VDDIO and VDDCORE Power Supply APMC ADC
32.768 kHz XTAL RTC Battery Power Supply Serial Ports RS232 Transceivers DB9 Serial Connectors
1-2

EBI
Clock Generator
AMBA Bridge APB
I 2C E2PROM
LEDs
Interrupt Controller
PIO
Watchdog Timer
Timer Counters Serial Data Flash Serial E2PROM
I/O Expansion Connector
Reset
SPI
Temperature Sensor
VDDCORE 2
DAC
AT91EB55 Evaluation Board User Guide
Section 2 Setting Up the AT91EB55 Evaluation Board
2.1
Electrostatic Warning
The AT91EB55 Evaluation Board is shipped in protective anti-static packaging. The board must not be subjected to high electrostatic potentials. A grounding strap or similar protective device should be worn when handling the board. Avoid touching the component pins or any other metallic element. Requirements in order to set up the AT91EB55 Evaluation Board are: the AT91EB55 Evaluation Board itself
2.2
Requirements
2.3
Layout
AT91EB55 Evaluation Board User Guide

DC power supply capable of supplying 7V to 12V @ 1 A (not supplied)
Figure 2-1 shows the layout of the AT91EB55 Evaluation Board. Figure 2-1. Layout of the AT91EB55 Evaluation Board
128K x 8 512K x 8
128K x 8 512K x 8
AT91M55800A 33 AI
2-1
Setting Up the AT91EB55 Evaluation Board
2.4
Jumper Settings
JP1 is used to boot on standard or user programs. For standard operations, set it in the STD position. JP8 is used to select the core power supply of the AT91M55800A. Operations at 2V are not supported on the current silicon. For more information about jumpers and other straps, see Appendix A.
2.5
Powering Up the Board
DC power is supplied to the board via the 2.1 mm socket (J1) shown below in Figure 22. The polarity of the power supply is not critical. The minimum voltage required is 7V. Figure 2-2. 2.1 mm Socket
positive (+) or negative (-)
2.1 mm connector
The board has a voltage regulator providing +3.3V. The regulator allows the input voltage to be from 7V to 12V. When you switch the power on, the red LED marked "POWER" will light up. If it does not, switch off and check the power supply connections. The battery BT1 provides a 3V power supply to the Advanced Power Management Controller and the Real Time Clock (VDDBU). In order to power up this module, the user must first close the JP9 jumper.
2.6
Measuring Current Consumption on the AT91M55800A
The board is designed to generate the power for the AT91 product only through the jumpers JP5 (VDDIO), JP8 (VDDCORE) and JP9 (VDDBU). This feature enables measurements to be made on the current consumption of the AT91 product. See Appendix A for further details.
2.7
Testing the In order to test the AT91EB55 Evaluation board, the following procedure should be performed: AT91EB55 Evaluation Board 1. Hold down the SW1 button and power up the board or generate a reset and wait
for the light sequence on each LED to complete. All the LEDs light once and the D1 LED remains lit. 2. Release the SW1 button. The LEDs D1 to D7 light up in sequential order. If an error is detected, all the LEDs will light up twice. The LEDs represent the following devices: D1 for the internal SRAM
If a test is not carried out, the corresponding LED remains unlit and the test sequence restarts. AT91EB55 Evaluation Board User Guide 2-2

D2 for the external SRAM D3 for the external Flash D4 for the E2PROM with I2C access D5 for the SPI data flash D6 for the SPI E2PROM D7 for the USART D8 for the ADC and DAC
Section 3 The On-board Software
3.1
AT91EB55 The AT91EB55 Evaluation Board contains an AT49BV16X4 Flash device programmed Evaluation Board with default software. Only the lowest eight 8-Kbyte sectors are used. The remaining
sectors are user-definable and can be programmed using one of the Flash downloader solutions offered in the AT91 library. When delivered, the Flash device contains: The Boot Software Program
The boot, FTS and SRAM downloader are in sectors 0 and 1 of the Flash. These sectors are not locked for an easy on-board upgrade. The user must avoid overwriting this sector.
3.2
The Boot Software Program
As long as the SW2 button is pressed: All the LEDs light together
When the SW4 button is pressed: The shutdown function from AT91M55800A is activated. The power-up can be achieved by pressing the S1 push button only (Wake-up function)
AT91EB55 Evaluation Board User Guide

The Functional Test Software The SRAM Downloader The Angel Debug Monitor A Default User Boot with a Default Application
The Boot Software Program configures the AT91M55800A and thus controls the memory and other board devices. The Boot Software Program is started at reset if JP1 is in the STD position. If JP1 is in the USER position, the AT91M55800A boots from address 0x01010000 in the Flash, which must have a user-defined boot. The Boot Software Program first initializes the master clock frequency at 32 MHz, the EBI, then executes the REMAP and checks the state of the buttons as described below. As long as the SW1 button is pressed: All the LEDs light together The D1 LED remains lit until SW1 is released The Functional Test Software (FTS) is started
The D2 LED remains lit until SW2 is released The SRAM downloader is activated
3-1
The On-board Software When no buttons are pressed: Branch at address 0x01004000
3.3
Programmed Default Memory Mapping
3.4
The SRAM Downloader
3.5
The Angel Debug The Angel Debug Monitor is located in the flash from 0x01004000 up to 0x0100FFFF. The boot program starts it if no button is pressed. Monitor
When Angel starts, it recopies itself in SRAM in order to run faster. The SRAM used by Angel is from 0x02020000 to 0x0203FFFF, i.e., the highest half part of the SRAM. The Angel on the AT91EB55 can be upgraded regardless of the version programmed on it. Note: If the debugger is started through ICE while the Angel monitor is on, the Advanced Interrupt Controller (AIC) and the USART channel are enabled.
3-2

The Angel Debug Monitor starts from this address by recopying itself in external SRAM
The following table defines the mapping defined by the boot program. Table 1. Memory Map
Part Name U1 U2 - U3 Start Address 0x01000000 0x02000000 End Address 0x011FFFFF 0x0203FFFF Size 2-Mbyte 256-Kbyte Device Flash AT49BV16X4 SRAM
The Boot Software Program, FTS and SRAM downloader are in sectors 0 and 1 of the Flash device. Sectors 2 to 7 support the Angel Debug Monitor Sector 24 at address 0x01100000 must be programmed with a boot sequence to be debugged. This sector can be mapped at address 0x01000000 (or 0x0 after a reset) when the jumper JP1 is in the USER position. The SRAM downloader allows an application to be loaded in the SRAM at the address 0x02000000 and then activates it. The boot starts it if the SW2 button is pressed at reset. The procedure is as follows: 1. Connect the AT91EB55 Evaluation Board to the host PC serial A connection using the straight serial cable provided. 2. Power on or press RESET, simultaneously holding down the SW2 button. Wait for D2 to light up and then release SW2. 3. Start the BINCOM utility, available in the AT91 Library, on the host computer: Select the communication port (COM1 or COM2, depending on where the serial cable is connected to the host PC) and the baud rate for communications (115200 baud, 1 stop bit, no parity), then open the file to be downloaded and send it. Wait for the transfer to end. 4. Press any button to end the download. The control is switched to the address 0x02000000.
AT91EB55 Evaluation Board User Guide
Section 4 Circuit Description
4.1
AT91M55800A Processor
Figure 1 in "Appendix B - Schematics" shows the AT91M55800A. The footprint is for a 176-pin TQFP package. Strap CB15 enables the user to choose between the standard ICE debug mode and the JTAG boundary scan mode of operation. The operating mode is defined by the state of the JTAGSEL input detected at reset. Jumper JP5 can be removed by the user to allow measurement of the current demand by the whole microcontroller (VDDIO and VDDCORE). Jumper JP8 can be removed to measure the core microcontroller consumption (VDDCORE). See Figure 8 in "Appendix B - Schematics." Jumper JP9 can be removed by the user to allow measurement of the current demand by the APMC and RTC microcontroller modules (VDDBU). See Figure 8 in "Appendix B - Schematics."
4.2
Expansion Connectors and JTAG Interface
The two expansion connectors (I/O expansion connector and EBI expansion connector) and the JTAG Interface are described below. The I/O and EBI expansion connectors pin-outs and positions are compatible with the other evaluation boards (except for the I/O expansion connector pin-out and position of the EB40) so that users can connect their prototype daughter boards to any of these evaluation boards. For the I/O expansion connector, rows A and B are position and pinout compatible. The I/O expansion connector makes the general purpose I/O (GPIO) lines, VCC3V3 and Ground available to the user. Configuration straps CB2, CB3, CB4, CB5, CB6, CB13, CB14 and CB17 are used to select between the I/O lines being used by the evaluation board or by the user via the I/O expansion connector. The connector is not fitted at the factory; however, the user can fit any 32 x 3 connector on a 0.1" (2.54 mm) pitch. The schematic illustrated in Figure 4 in "Appendix B - Schematics" also shows the Bus expansion connector, which, like the I/O expansion connector, is not fitted at the factory. The user can fit any 32 x 2 connector on a 0.1" (2.54 mm) pitch to gain access to the data, address, chip select, read/write, oscillator output and wait request pins. VCC3V3 and Ground are also available on this connector. Configuration strap CB1, when open, allows the user to connect the EBI expansion connector to the MPI expansion connector of an AT91EB63 evaluation board without fearing any conflict problem. An ARM-standard 20-pin box header (P5) is provided to enable connection of an ICE to the JTAG inputs on the AT91. This allows code to be developed on the board without using system resources such as memory and serial ports. 4-1
4.2.1
I/O Expansion Connector
4.2.2
EBI Expansion Connector
4.2.3
JTAG Interface
AT91EB55 Evaluation Board User Guide
Circuit Description
4.3
Memories
The schematics in Figures 3 and 9 in "Appendix B - Schematics" show one AT49BV16X4 2-Mbyte 16-bit Flash, one AT24C512 64-Kbyte EEPROM, one AT25256 32-Kbyte EEPROM, two 128K/512K x 8 SRAM devices and four AT45DB321 4-Mbyte serial data Flash devices. The SPI devices are accessible through a 4 to 16 line decoder and by using the Chip Select Decode feature of the AT91 SPI peripheral (PCSDEC bit of the SPI Mode Register).
Note: The AT91EB55 is fitted with two 128K x 8 SRAM devices and one AT45DB321 serial DataFlash device (U21).
The AT91EB55 may be fitted with a Flash using either an AT49BV1604 (CB18 should be closed) or an AT49BV1614 (CB18 should be open). Strap JP1 shown on the schematic is used to select which part of 1-Mbyte of the flash is to be accessed. This is to enable users to flash download their application in the second part of the flash and to boot on it.
4.4
ADC and DAC Peripheral Connections
Two of the ADC and DAC channels are loop-backed together: DA0 on AD4 and DA1 on AD0. Two 2.5V voltage reference devices are fitted on the board and connected to the DAVREF and ADVREF inputs, See Figures 6 in "Appendix B - Schematics". The user can fit other voltage reference value devices from this family (REF19x from Analog Devices) as the footprints are compatible. A temperature sensor (LM61: figure 6 in "Appendix B - Schematics") is connected to the AD1 input and is placed near the 32.768 kHz crystal quartz. It enables the user to take into account the frequency drift due to temperature evolutions using a software program. The VDDCORE with a resistor bridge (10 k) provides the following value:
VDDCORE ----------------------------2
This voltage can be measured by AD2 input and allows the user to select the running clock accordingly.
4.5
Power and Crystal Quartz
The board features two quartz crystals: a 32.768 kHz one connected to the RTC lowpower oscillator of the AT91M55800A and a 16 MHz one connected to the main oscillator. The AT91M55800A Master Clock can be derived from the 32.768 kHz crystal quartz or the 16 MHz crystal quartz depending on the programming of the APMC registers. The on-chip oscillators together with one PLL-based frequency multiplier and the prescaler results in a programmable Master Clock between 500 Hz and 33 MHz. Components for the PLL filter are fitted by default on the board (Figure 6 in "Appendix B - Schematics"). They are calculated to provide a 32 MHz (multiplier factor of 2 and settling time of 160 s) Master Clock frequency. The Voltage Regulator provides 3.3V to the board and will light the red POWER LED (D11) when operating. This Voltage Regulator can be turned off by using the APMC shutdown feature when the JP7 jumper is closed. See Figure 8 in "Appendix B - Schematics." A wake-up push button (S1) is provided to exit this mode. Alternatively, the user can program a RTC alarm to awake the voltage regulator.
4-2
AT91EB55 Evaluation Board User Guide
Circuit Description Power can be applied via the 2.1 mm connector to the regulator in either polarity because of the diode rectifying circuit. Another regulator allows the user to power the AT91M55800A core with 3.3V or 2V by the mean of the JP8 jumper. A 3V battery is provided on-board (Figure 8 in "Appendix B - Schematics") to power the RTC and APMC (VDDBU). It has been provided to ensure the power supply for approximately 1 year.
4.6
Push Buttons, LEDs, Reset and Serial Interface
The IRQ0, TIOA0, PB17 and PB19 switches are debounced and buffered. A supervisory circuit has been included in the design to detect and, consequently, reset the board when the 3.3V supply voltage drops below a typical 3.0V threshold. Note that the threshold can change, depending on the board production series. The supervisory circuit also provides a debounced reset signal. This device can also generate the reset signal in case of watchdog timeout as the pin NWDOVF of the AT91M55800A is connected on its input MR. The assertion of this reset signal will light the red RESET LED D10 and if the CLEAR RESET push button is pressed the LED D10 will unlight. Another supervisory circuit separately initializes the microcontroller embedded JTAG/ICE interface when the 3.3V supply voltage drops below a typical 3.0V threshold. Note that this voltage can change depending on the board production series. The separated reset lines allow the user to reset the board without resetting the JTAG/ICE interface while debugging. bill An RC device has been fitted on-board to ensure a correct power-on reset for the battery power supply modules (V D D B U ) first power up or when V D D B U has been disconnected. This RC network has been calculated to generate a valid 300 ms minimum pulse width NRSTBU signal. The schematic Figure 5 in "Appendix B - Schematics" also shows eight general-purpose LEDs connected to Port B PIO pins PB8 to PB15. Two 9-way D-type connectors P3/4 are provided for serial port connection. Serial Port A (P3) is used primarily for host PC communication and is a DB9 female connector. TXD and RXD are swapped so that a straight through cable can be used. CTS and RTS are connected together as are DCD, DSR and DTR. Serial Port B (P4) is a DB9 male connector with TXD and RXD obeying the standard RS-232 pin-out. Apart from TXD, RXD and Ground, the other pins are not connected. A MAX3223 device U10 and associated bulk storage capacitors provide RS-232 level conversion.
4.7
Layout Drawing
The layout diagram schematic shows an approximate floorplan for the board. This has been designed to give the lowest board area, while still providing access to all test points, jumpers and switches on the board. See Figure 1 in "Appendix B - Schematics." The board is provided with four mounting holes, one at each corner, into which feet are attached. The board has two signal layers and two power planes.
AT91EB55 Evaluation Board User Guide
4-3
Circuit Description
4-4
AT91EB55 Evaluation Board User Guide
Section 5 Appendix A - Configuration Straps
5.1
Configuration By adding the I/O and EBI expansion connectors, users can connect their own peripherStraps (CB1 - 15, als to the evaluation board. These peripherals may require more I/O lines than available while the board is in its default state. Extra I/O lines can be made available by disabling JP1 - 9)
some of the on-board peripherals or features. This is done using the configuration straps detailed below. Some of these straps present a default wire (notified by the default mention) that must be cut before soldering the strap.
CB1 Closed Open
(1)
On-board NCS4 Signal NCS4 signal is connected to the EBI expansion connector (P1 - B21) NCS4 signal is not connected to the EBI expansion connector (P1 - B21). This authorizes users to connect the EBI expansion connector of this board to the MPI expansion connector of an AT91EB63 evaluation board without conflict problems.
CB2 Closed Open
(1)
ADC0 Trigger Input Command ADC0 trigger input (AD0TRIG) is controlled by the PA4 PIO line. ADC0 trigger input (AD0TRIG) is not connected to the PA4 PIO line. This authorizes users to connect the corresponding lines to their own resources via the I/O expansion connector.
CB3 Closed Open
(1)
ADC1 Trigger Input Command ADC1 trigger input (AD1TRIG) is controlled by the PA7 PIO line. ADC1 trigger input (AD1TRIG) is not connected to the PA7 PIO line. This authorizes users to connect the corresponding lines to their own resources via the I/O expansion connector.
AT91EB55 Evaluation Board User Guide
5-1
Appendix A - Configuration Straps
CB4 Closed(1) Open
Temperature Sensor Enabling The temperature sensor device is connected to the ADC channel 1 (AD1) input. The temperature sensor device is not connected to the ADC channel 1 (AD1) input. This authorizes users to connect the corresponding ADC channel to their own resources via the I/O expansion connector.
CB5 Closed(1) Open
Analog Converter Peripherals Loopback DAC Channel 0 is connected to ADC Channel 4 for test purposes. DAC Channel 0 is not connected to ADC Channel 4. This authorizes users to connect the corresponding Analog Channels to their own resources via the I/O expansion connector.
CB6 Closed Open
(1)
Analog Converters Peripherals Loopback DAC Channel 1 is connected to ADC Channel 0 for test purposes. DAC Channel 1 is not connected to ADC Channel 0. This authorizes users to connect the corresponding Analog Channels to their own resources via the I/O expansion connector.
CB9 Closed Open
(1)
On-board Boot Chip Select NCS0 select signal is connected to the Flash memory. NCS0 select signal is not connected to the Flash memory. This authorizes users to connect the corresponding select signal to their own resources via the EBI expansion connector.
CB10 Closed(1) Open
Flash Reset The on-board reset signal is connected to the Flash RESET input. The on-board reset signal is not connected to the Flash RESET input.
CB11 Open Closed(1)
Boot Mode Strap Configuration The BMS MCU input pin is set in order for the microcontroller to boot on an external 16-bit memory at reset. The BMS MCU input pin is set in order for the microcontroller to boot on an external 8-bit memory at reset.
5-2
AT91EB55 Evaluation Board User Guide
Appendix A - Configuration Straps
CB13, CB14 Closed(1) Open
I2C EEPROM Enabling E2PROM communication is enabled. E2PROM communication is disabled. This authorizes users to connect the corresponding PIO to their own resources via the I/O expansion connector.
CB15 1-2 2-3
(1)
JTAGSEL The MCU standard ICE debug feature is enabled. IEEE 1149.1 JTAG boundary scan feature is enabled.
CB16 1-2 2 - 3(1)
R(eturn) TCK ICE Signal Synchronization The TCK signal from the JTAG interface can be synchronized with MCKO signal and returns to the JTAG interface. (RTCK) The TCK and RTCK ICE signals are not synchronized with MCKO.
CB17 Closed(1) Open
VDDCORE Voltage Measurement The VDDCORE power supply is connected to the ADC Channel 2 (AD2) input through a resistor bridge (divisor ratio 1/2). The VDDCORE power supply is not connected to the ADC Channel 2 (AD2) input. This authorizes users to connect the corresponding ADC Channel to their own resources via the I/O expansion connector.
CB18 Open Closed
Flash Configuration Should be open when an AT49BV1614 is fitted on the board. Should be closed when an AT49BV1604 is fitted on the board.
JP1 2-3 1-2
User or Standard Boot Selection The first half of the Flash memory is accessible at its base address. The second half of the Flash memory is accessible at its base address. This authorizes users to download their own application software in this part and to boot on it.
AT91EB55 Evaluation Board User Guide
5-3
Appendix A - Configuration Straps
JP2 Open Closed
Push Button Enabling SW1-4 inputs to the AT91 are valid. SW1-4 inputs to the AT91 are not valid. This authorizes users to connect the corresponding PIO to their own resources via the I/O expansion connector.
JP3 Open Closed
RS-232 Driver Enabled The RS-232 transceivers are enabled. The RS-232 transceivers are disabled. This authorizes users to connect the corresponding PIO to their own resources via the I/O expansion connector.
JP7 Open Closed
Power Shut-down Feature The power supply shut-down feature is disabled. The power supply shut-down feature is enabled. The user may shut-down the board main power supply by using the APMC shut-down feature. The system may be awakened by pushing the S1 Wake-Up push button or by programming an alarm in the RTC module.
JP8 2-3 1-2 Notes:
Core Power Supply Selection The MCU core is powered by a 3.3V power supply. Not supported on the current microcontroller revision. 1. Hardwired default position: To cancel this default configuration, cut (or place) the wire (a jumper) on the board.
5.2
Power Consumption Measurement Straps (JP5, JP9)
The JP5 strap enables the user to connect an ammeter to measure the AT91M55800A global consumption (VDDCORE and VDDIO) when VDDCORE power supply is derived from VDDIO (JP8 in 3V3 position). The user can measure the core consumption by connecting another ammeter between JP8 1 - 2 or 2 - 3 depending on the power supply used to power the core. The JP9 strap enables the user to connect an ammeter to measure the AT91M55800A APMC and RTC modules battery backup consumption (VDDBU).
5.3
Ground Links (JP6)
The JP6 strap allows the user to connect the electrical and mechanical ground.
5-4
AT91EB55 Evaluation Board User Guide
Appendix A - Configuration Straps
5.4
Increasing Memory Size
The AT91EB55 evaluation board is supplied with two 128K bytes x 8 SRAM memories. If, however, the user needs more than 256K bytes of memory, the devices can be replaced with two 512K x 8, 3.3V, 10/15 ns SRAMs, giving in total 1024K bytes. The AT91EB55 evaluation board is supplied with one 4-MB Serial Data Flash. If the user needs more storage memory, 3 additional footprints are provided to fit AT45DB321 devices giving a total of 16M bytes.
AT91EB55 Evaluation Board User Guide
5-5
Appendix A - Configuration Straps
5-6
AT91EB55 Evaluation Board User Guide
Section 6 Appendix B - Schematics
6.1
Schematics
The following schematics are appended: Figure 6-1 PCB Layout
AT91EB55 Evaluation Board User Guide

Figure 6-2 AT91EB55 Blocks Synopsis Figure 6-3 EBI Memories Figure 6-4 I/O and EBI Expansion Connectors Figure 6-5 Push Buttons, LEDs and Serial Interface Figure 6-6 AT91M55800A Figure 6-7 Reset and JTAG Interface Figure 6-8 Power Supply Figure 6-9 SPI and I2C Memories
The pin connectors are indicated on the schematics: P1 = EBI Expansion - External Bus Interface (Figure 6-4) P2 = I/O Expansion Connector (Figure 6-4) P3 = Serial A - Serial Interface (Figure 6-5) P4 = Serial B- Serial Interface (Figure 6-5) P5 = JTAG Interface (Figure 6-7)
6-1
Appendix B - Schematics Figure 6-1. PCB Layout
128K x 8 512K x 8
128K x 8 512K x 8
AT91M55800A 33 AI
6-2
AT91EB55 Evaluation Board User Guide
MICRCONTROLLOR MICROCONTROLLER
MOSI MISO SPCK
SDA SCL
AT91EB55 Evaluation Board User Guide 6-3
Figure 6-2. AT91EB55 Blocks Synopsis
EBI_[0..49]
EBI MEMORIES
IOB_54
IOB_54
EBI_[0..49] IOB_[0..71]
EBI_[0..49] IOB_[0..71]
NPCS[0..3]
MOSI MISO SPCK SDA SCL
EBI_41 IOB_[68..71]
EBI_41
SERIAL MEMORIES
IOB_[68..71]
NPCS[0..3] MOSI MISO SPCK SDA SCL SERIAL MEMORIES
memories connected on EBI
MOSI MISO SPCK SDA SCL
INPUT / OUTPUT ON BOARD
NPCS[0..3]
IOB_[0..67]
NPCS[0..3] IOB_[0..67] EBI_[0..49]
IOB_[0..71] EBI_[0..49]
IOB_[0..71]
IOB_[0..53]
IOB_[0..53]
SHDN micro / Rst / Wchdog / JTAG co.
SHDN
Serial Connectors / P.B. / LED
SUPPLY and RTC SAVE
SHDN
SHDN
Extension Connectors
IOB_[0..71] EBI_[0..49]
IOB_[0..71]
EBI_[0..49]
power supply / battery
Extension Connectors
Appendix B - Schematics
Title Size
EVALUATION BOARD FOR AT91M55200/800
Document Number
Rev
A4 SYNOPSIS
Date:
5
Sheet
Monday, December 18, 2000
1
of
8
1
NCS0 1 NWR0/NWE NRD/NOE 2 2 CE WE OE RESET GND GND 46 27 26 11 28 12 1 C5 100nF 2
VCC3V3 U4
512k
2
3
1 A19
1
2 74LVC04AD
1
6-4
U1
A[0..19] D[0..15] layout for SOJ 400mil.
U2 A18 A1 A2 A3 A4 A17 A16 A15 A14 D7 D6 D5 D4 NWR1/NUB VCC3V3 D10 D11 VCC3V3 NRD/NOE D8 D9 NCS1 D15 D14 D13 D12
128k 512k
U3 A18 A1 A2 A3 A4 A17 A16 A15 A14
128k 512k
Figure 6-3. EBI Memories
Appendix B - Schematics
NCS1 D0 D1 D2 D3 NWR0/NWE
NRD/NOE
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 (A-1) / I/O15 VCC3V3
29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
VCC3V3
A20B CB18 VCC3V3 R1 100k (BYTE) / VCCQ VCC C1 100nF C2 100nF C3 100nF NC / (A19) NC NC NC / Vpp 47 37 VCC3V3 VCC3V3 A19 A19 VCC3V3 VCC3V3
1
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 2 25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 / (RDY / BUSY) A5 A6 A7 A8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 A0 A1 A2 A3 A4 CS D0 D1 VCC GND D2 D3 WE A5 A6 A7 A8 A9 A13 A12 A11 A10 A9 A5 A6 A7 A8 A13 A12 A11 A10 A9 NC A18 A17 A16 A15 OE D7 D6 GND VCC D5 D4 A14 A13 A12 A11 A10 NC A0 A1 A2 A3 A4 CS D0 D1 VCC GND D2 D3 WE A5 A6 A7 A8 A9 NC A18 A17 A16 A15 OE D7 D6 GND VCC D5 D4 A14 A13 A12 A11 A10 NC 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
9 10 14 13
IDT71V424S10Y
IDT71V424S10Y
VCC3V3
CB9
C4 100nF
CB10
NRST
1
R2 100k
AT49BV1604-90TC
layout for TSSOP 400mil.
A18
U5
512k
A18
128k
IOB_54
IOB_54
AE20
STD BOOT
D0 D1 D2 D3 A5 A6 A7 A8 2 A20B NWR0/NWE VCC3V3
NCS1
A1 A2 A3 A4
A17 A16 A15 A14 D7 D6 D5 D4 A13 A12 A11 A10 A9
NRD/NOE
NCS1
A1 A2 A3 A4 D8 D9 VCC3V3 VCC3V3 D10 D11 NWR1/NUB A5 A6 A7 A8 A19
A17 A16 A15 A14 D15 D14 D13 D12 A13 A12 A11 A10 A9
NRD/NOE
JP1 jumper_3P U6A
VCC3V3
USER BOOT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 NC NC A0 A1 A2 A3 A4 CS D0 D1 VCC GND D2 D3 WE A5 A6 A7 A8 A9 NC NC NC NC 128k NC A18 A17 A16 A15 OE D7 D6 GND VCC D5 D4 A14 A13 A12 A11 A10 NC NC NC
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
NC NC A0 A1 A2 A3 A4 CS D0 D1 VCC GND D2 D3 WE A5 A6 A7 A8 A9 NC NC
NC NC NC A18 A17 A16 A15 OE D7 D6 GND VCC D5 D4 A14 A13 A12 A11 A10 NC NC NC
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
IDT71424S10PH
EBI_[0..15] EBI_[16..35] EBI_[36..41] CTL0 CTL1 CTL2 CTL5 NCS0 NCS1 EBI_[42..49] NWR1/NUB NRD/NOE NRST NWR0/NWE
IDT71424S10PH
D[0..15] A[0..19] CTL[0..5]
NCS[0..7]
EBI_[0..49]
Title Size Date:
EVALUATION BOARD FOR AT91M55200/800
Document Number Rev
A4 MEMORIES CONNECTED ON E.B.I.
Monday, December 18, 2000
Sheet
5
2
of
AT91EB55 Evaluation Board User Guide
8
EBI Extension Connector
NCS[0..7] PA[0..25] PB[0..27]
P2A P2B P2C
I/O Extension Connector
CTL[0..5]
P1A P1B
CTL0 CTL2 CTL4 CTL1 CTL3 PA9 PA10 PA11 PA12 PA13 VCC3V3 PB3 PB4 PB5 PB0 VCC3V3 VCC3V3 VCC3V3 NCS1 NCS3 CTL5 A1 A3 A5 A7
NCS0 NCS2
A0 A2 A4 A6
VCC3V3
PB13 PB14 PB15 PB16 PB17 VCC3V3 AE20 AE21 AE22 AE23 DA0 DA1 PB6
PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27
AE[20..23]
AT91EB55 Evaluation Board User Guide
A9 A11 A13 A15 VCC3V3 A17 A19 NCS6 CB1 2 NCS4 VCC3V3 PB10 PB11 PB12 PB18 D1 D3 D5 D7 VCC3V3 D9 D11 D13 D15 VCC3V3 NSPICS8 NSPICS7
A8 A10 A12 A14
DA[0..1]
Figure 6-4. I/O and EBI Expansion Connectors
VCC3V3
A16 A18 NCS7 NCS5 NSC4_1 1 PB1 PB2 PB8 PB9
D0 D2 D4 D6
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 NSPICS5 NSPICS6 PB7
D8 VCC3V3 D10 D12 D14
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 GND NWR0 / NWE NRD / NOE MCK0 NCS0 NCS2 VCC3V3 A0 / NLB A2 A4 A6 GND A8 A10 A12 A14 VCC3V3 A16 A18 NCS7 NCS5 GND D0 D2 D4 D6 VCC3V3 D8 D10 D12 D14 GND PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA24 PA25 PA23 EBI Ext. Con. EBI Ext. Con. I/O Ext. Conn. I/O Ext. Conn. I/O Ext. Conn. GND NWR1 / NUB NWAIT NCS1 NCS3 NRST A1 A3 A5 A7 GND A9 A11 A13 A15 VCC3V3 A17 A19 NCS6 NCS4 GND D1 D3 D5 D7 VCC3V3 D9 D11 D13 D15 GND GND VCC3V3 PA9 / IRQ0 PA10 / IRQ1 GND PA11 / IRQ2 VCC3V3 PA12 / IRQ3 GND PA13 / FIQ VCC3V3 PB3 / IRQ4 PB4 / IRQ5 GND PB5 / IRQ6 PB0 GND PB1 PB2 PB8 PB9 VCC3V3 PB10 PB11 PB12 PB18 / BMS GND NSPICS8 NSPICS7 GND VCC3V3 GND PB19 / TCLK0 PB20 / TIOA0 PB21 / TIOB0 PB22 / TCLK1 PB23 / TIOA1 PB24 / TIOB1 PB25 / TCLK2 PB26 / TIOA2 PB27 / TIOB2 PA0 / TCLK3 PA1 / TIOA3 PA2 / TIOB3 PA3 / TCLK4 PA4 / TIOA4 PA5 / TIOB4 PA6 / TCLK5 PA7 / TIOA5 PA8 / TIOB5 PA14 / SCK0 PA15 / TXD0 PA16 / RXD0 PA17 / SCK1 PA18 / TXD1 / NTRI PA19 / RXD1 PA20 / SCK2 PA21 / TXD2 PA22 / RXD2 PA24 / MISO PA25 / MOSI PA23 / SPCK NSPICS5 NSPICS6 GND VCC3V3 PB13 PB14 PB15 PB16 PB17 VCC3V3 GND A20 A21 A22 A23 GND DA0 GND DA1 GND PB6 / AD0TRIG GND AD0 AD1 AD2 AD3 GND AD4 AD5 AD6 AD7 GND PB7 / AD1TRIG GND
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32
AD[0..7] NSPICS[5..8]
IOB_[68..71]
D[0..15] A[0..19] CTL[0..5] NCS[0..7] EBI_[42..49] EBI_[36..41] EBI_[16..35]
EBI_[0..15]
AD[0..7] DA[0..1] AE[20..23] EBI_[0..49] PB[0..27] PA[0..25]
IOB_[60..67]
IOB_[58..59]
IOB_[54..57]
IOB_[26..53]
IOB_[0..71]
IOB_[0..25]
Title
EVALUATION BOARD FOR AT91M55200/800
Size Date: Document Number Rev
A4 Extension Connectors
Monday, December 18, 2000
Sheet
5
3
of
8
Appendix B - Schematics
6-5
2
VALBP 1 VALBP R5 100k TP 33 C10 47nF PB9 VCC3V3 VCC3V3 VCC3V3 U9 1 2 4 6 8 12 D4 R9 100R 14 D3 R8 100R 16 D2 R7 100R SW2 PB10 IRQ0 TIOA0 19 PB11 C11 47nF R42 100k PB8 VCC3V3 2 18 D1 R6 100R R43 100k 1
TP 33
7
14
10
100nF C13
R44 100k
R45 100k
74LV244D
20
TP 33
18
19
VCC
GND
2
1
6-6
PA[0..25]
IOB_[0..25] VCC3V3 VCC3V3
VCC3V3
PB[0..27]
IOB_[26..53] IOB_[0..53] U8 JP2 jumper_NO VCC3V3
R3 100K
R4 100K
EN
Red LED
Appendix B - Schematics
SW1
74LV125D
3 PA9 PB20 6
EN EN
9 7 5 GND SIGNAL VCC3V3 VCC3V3 VCC3V3 100nF 3 D8 D7 D6 R11 R12 R13 D5 R10 100R 100R 100R 100R 8 PB17 PB19 PB14 PB15 VCC3V3 17 15 PB13 13 PB12 11 C12 2 11
4 5 10 9 VCC3V3 13 12
VCC3V3 VCC3V3 VCC3V3 VCC3V3
VCC3V3
Figure 6-5. Push Buttons, LEDs and Serial Interface
R14 100K 1
R15 100K
SW3 VCC3V3 C16 VCC3V3 100nF C17 V+ C19 V7 100nF 3 100nF
C14 47nF
SW4 TP 33 C15 47nF
P3 DCD0 DSR0 TX0 RX0 DTR0 C20 22pF RTS0 CTS0
R16 100k C18 100nF 4 C1C2+ C2T1IN T2IN R1OUT R2OUT EN FORCEON U10 R1IN R2IN INVALID FORCEOFF 16 9 11 20 T1OUT T2OUT 17 8 5 6 13 12 15 10 1 14 2 C1+
Usart 0: SERIAL A
C21 22pF
PA[0..25]
C22 100nF VCC3V3 PA15 PA18 PA16 PA19 RXD0 RXD1 TXD0 TXD1
PA9
1 6 2 7 3 8 4 9 5 Sub D 9b F C25 C23 22pF C24 22pF 10nF P4
JP3 jumper_NO
RX1
R17 100K
MAX3223ECAP
VCC3V3
TX1 C26 22pF C27 22pF
1 6 2 7 3 8 4 9 5 Sub D 9b M
Usart 1: SERIAL B
Title
EVALUATION BOARD FOR AT91M55200/800
Size Date: Document Number Rev
A4 Serial Connectors / P.B. /LED
Monday, December 18, 2000
Sheet
5
4
of
AT91EB55 Evaluation Board User Guide
8
BMS PB18 R46 100k
JTAG[0..4]
JTAG[0..4]
EBI_[0..15] EBI_[16..35]
PB[0..27]
CTL3 VCC3V3 NWAIT
D[0..15] A[0..19] EBI_[0..49] CTL[0..5]
EBI_[36..41] EBI_[42..49]
R41 100K 2 VCC3V3
CTL[0..5] NCS[0..7]
C28 100nF CB2 PB6 PB7 CB3 VDDA CB4 GNDA GNDA GNDA 100nF 100nF 2 C32 C33 1F / 16V VCC3V3 CB12 1 VDDA C41 SHDN 10F / 16V vt NRSTBU WAKEUP GNDBU 1 2 VDDA GNDA GNDA 100nF VDDA GNDA VDDA vt R48 100k C38 C31 U14 DA1 DA0 DAVREF ADVREF AD1 1 2 2 Vout LM61BIM3 AD1TRIG 1 2 PA7 TIOA5 1 VDDCORE AD0TRIG 1 2 PA4 TIOA4 U13 VCC GND 3 C91 100nF CTL4 JTAGSEL NWDOVF CTL5 MCKO JTAGSEL NWDOVF NRST
PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7
PB18
PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17
1 CB11
JTAGSEL JTAG2 JTAG1 JTAG4 JTAG3 JTAG0
CTL4
VDDIO
VDDIO
Default boot Mode : 16 Bits
VDDCORE VDDCORE
NCS[0..7]
CTL5 CTL3 CTL2 CTL0 CTL1 NCS4 NCS5 NCS6 NCS7
C29 134 133 100nF VDDIO
NWDOVF
176 175
174 173 172 171 170
169 168 167 166 165 164
163
162 161
160
159
158 157 156 155 154 153 152 151 150 149
148 147
146 145 144 143 142 141 140 139
PB17 PB16 PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8
MCKO
NTRST TCK TDO TDI TMS JTAGSEL
NWDOVF
VDDIO VDDCORE
PB18 / BMS
Figure 6-6. AT91M55800A
C30 100nF VDDIO VDDCORE GNDA DA1 DA0 DAVREF ADVREF 127 126 129 128 130 132 131 VDDIO VDDCORE 1 2 GND GND
GND VDDIO
GND VDDIO
NCS7 NCS6 NCS5 NCS4
GND GND
A[0..19]
NUB / NWR1 NWE / NWRO NOE / NRD NWAIT NRST PB7 / AD1TRIG PB6 / AD0TRIG PB5 / IRQ6 PB4 / IRQ5 PB3 / IRQ4 PB2 PB1 PB0
138 137 136 135
VDDIO
VDDIO
NCS[0..7]
GNDA
NCS0 NCS1 NCS2 NCS3 NCS0 NCS1 NCS2 NCS3
3 4 5 6
REF 2.5V
TP NC Vs NC SLEEP OUTPUT GND TP DAVREF C37 100nF C36 REF192GS U15
1
2
WAKEUP GND
114 113
2
AT91M55_TQFP176 U12 AT91M55800A - 33AI
112 NRSTBU 111 XOUT32 110 XIN32 109 VDDBU
R18 270K XOUT32 XIN32
GND
1
A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 PLLRC 108 PLLRC GNDPLL C45 VDDIO VDDIO GND 29 30
17 18 19 20 21 22 23 24 25 26 27 28
1 R20 287R 1% 1 2 1 1 C46 68pF 10% 2 VDDPLL 103 102 680pF 10% 2
2 C44 1
GNDBU 2 2 CB7 C47 1 2 2 Y4 Qtz 16MHz XOUT XIN VDDIO 1 Osc 16MHZ Y3 3 OUT NC/ENABLE GND GNDBU 107 106 105 104 4 C92 100nF VDDBU 1 R21 100k
AE[20..23]
31 32 33 34 A20 A21 A22 A23
AE20 AE21 AE22 AE23
GNDPLL XOUT XIN VDDPLL
GND VDDIO
C48 1 2 1 NPCS3 NPCS2 NPCS1 NPCS0 PA25 PA24 PA23 NPCS[0..3] VDDCORE R56 100K PA22 / RXD2 PA21 / TXD2 PA20 / SCK2 PA19 / RXD1 GND GND 94 93 92 91 90 89 PA22 PA21 PA20 PA19 1 CB17 2 CB8 2
2
4
VCC
VCC
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
35 36 37 38 39 40 41 42
8 7 6 5 8 7 6 5
VDDCORE 43 44 VDDIO VDDCORE VDDIO RR2
100k
PA29 / NPCS3 PA28 / NPCS2 PA27 / NPCS1 PA26 / NPCS0 / NSS PA25 / MOSI PA24 / MISO PA23 / SPCK
101 100 99 98 97 96 95
RR1
100k
1 2 3 4 1 2 3 4
TCLK3 TIOA3 TIOB3 TCLK4 TIOA4 TIOB4 TCLK5
VDDIO
C49 GND GND D8 D9 D10 D11 D12 D13 D14 D15 VDDIO GND C50 100nF 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 100nF
PA[0..25]
VDDIO GND VDDCORE VDDIO
PB19 / TCLK0 PB20 / TIOA0 PB21 / TIOB0 PB22 / TCLK1
PB23 / TIOA1 PB24 / TIOB1 PB25 / TCLK2 PB26 / TIOA2 PB27 / TIOB2
PA0 / PA1 / PA2 / PA3 / PA4 / PA5 / PA6 /
VCC3V3
PA7 / TIOA5 PA8 / TIOB5 PA9 / IRQ0 PA10 / IRQ1 PA11 / IRQ2 PA12 / IRQ3 PA13 / FIQ PA14 / SCK0 PA15 / TXD0 PA16 / RXD0 PA17 / SCK1 PA18 / TXD1 / NTRI
66 67 68 69 70 71 72
73 74
75 76 77 78 79 80 81 82 83 84 85 86
VDDCORE
87 88
VDDIO VDDCORE
C51 100nF VDDIO VDDCORE
VDDIO
VDDIO
D15 D14 D13 D12 D11 D10 D9 D8
100k
VCC3V3
1 RR3 2 3 4 1 2 3 4 8 7 6 5 8 7 6 5 RR4
100k
PB[0..27]
SDA SCL
PA[0..25]
D[0..15]
+
AT91EB55 Evaluation Board User Guide
7 8 9 10 11 12 13 14 CB6 A0/NLB A1 A2 A3 A4 A5 A6 A7 VDDA 117 116 115 VDDIO GND VDDIO 15 16 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 125 124 123 122 121 120 119 118 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
A0 A1 A2 A3 A4 A5 A6 A7 CB5
1 2 3 4
8 7 6 5
U12
GNDBU SHDN
VDDBU
Title Size
A4
Date:
+
C42 100nF MOSI MISO SPCK
+
1F / 16V GNDA
REF 2.5V
TP NC Vs NC SLEEP OUTPUT GND TP REF192GS ADVREF 100nF C39 C40
1 2 3 4
8 7 6 5
+
1F / 16V GNDA Y1 osc 32,768KHz C43 1 2 GNDBU Y2 Qtz 32,768kHz 3 OUT NC/ENABLE 1 R19 100k
C93 100nF VDDPLL
R57 100K
AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 DA1 DA0
AD[0..7]
IOB_[60..67]
DA[0..1] AE[20..23] PB[0..27] PA[0..25]
PA6 PA5 PA4 PA3 PA2 PA1 PA0 PA18 PA17 PA16 PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7
IOB_[58..59] IOB_[54..57] IOB_[26..53] IOB_[0..25] IOB_[0..67]
PB27 PB26 PB25 PB24 PB23
PB22 PB21 PB20 PB19
EVALUATION BOARD FOR AT91M55200/800
Document Number
Microcontroller / Reset / Watchdog / JTAG connector Monday, December 18, 2000
Sheet
Rev
5
5
of
8
Appendix B - Schematics
6-7
CLRSTLED
14
7
RESET
SW5 TP 33
JTAGSEL
JTAGSEL
IEEE
2
3
1
U18 1 2 GND RST VCC MR 4 3 JTAG0 JTAG1 MAX6315US27D1-T JTAG2
R27 100k 1 3 5 7 TCK 9 11 13 NRST 15 17
P5 VCC NTRST TDI TMS TCK TCK TDO NRST NC NC HE10 2x10 VCC GND GND GND 2 4 6 8 10 12 14 16 18 20
3
1
14
7
GND GND
G8 G9 G7 C77 10nF C95
14
7
6-8
VCC3V3 VDDBU VCC3V3 R22 100k NWDOVF U6B 3 CTL6 4 3 2 1 10 11 12 13 U16
S C1 1D R
Figure 6-7. Reset and JTAG Interface
Appendix B - Schematics
5 6
D9 PBRST BAS216 R23 RSTLED 100R
R24 100R
R26 100k
NRST
1
74LVC04AD
4
CLKRSTLED
74LVC74AD
9 8
WAKEUP
VCC3V3 R54 100k C52 C53 U17 1 GND RST VCC MR 4 3 100nF VCC3V3 100nF R25 100k GNDBU CTL5 NRST
CLEAR RESET LED
S2 B.P.
RESET
D10 Red LED
3V3 SUPPLY
D11 Red LED
WAKEUP
S1 B.P.
VCC3V3
2
PBRST
MAX6315US27D1-T VCC3V3 CB15
ICE
13
U6F
1
74LVC04AD U6E
12
C94 100nF
VCC3V3
VCC3V3 C71 VCC3V3 TCK 11 JTAG3
CB16 2
1
74LVC04AD U6D
10
10nF MCKO 4 3 2 1 10 11 12 13
U30
S C1 1D R
G1 G2 G3 G4 G5 G6 G7
TCK
5 6
RTCK 9
1
74LVC04AD U6C 74LVC04AD
8
74LVC74AD
9 8
JTAG3 JTAG4 JTAG[0..4]
JTAG GND
GND GND
GND
AT91EB55 Evaluation Board User Guide
VCC3V3 C96 100nF
5
1
6
JTAG0 C78 10pF
JTAG1 C79 10pF
JTAG2 C80 10pF
JTAG3 C81 10pF
19
VCC3V3 100nF
JTAG4 C84 10pF
NRST C85 10pF
G1 C72 10nF G2 C74 10nF
G3 C76 10nF G4 C82 10nF
G5 C73 10nF G6 C75 10nF
G8 C83 10nF G9 C86 10nF
Title Size
EVALUATION BOARD FOR AT91M55200/800
Document Number of Rev
A4 RESET / JTAG / Watchdog Date: Sunday, July 09, 2000 Sheet
5 8 6
3
3 C61 1F 10% 2 5
C1+ C1SHDN/SS LT1503CS8-2
C2+ C2GND
6 8 7 C62 1F 10%
+ C63
10F / 16V
VDDCORE=2.0V
C64 1F 10% TP1 Test Point Corner 1 TP2 Test Point Corner 2
1
AT91EB55 Evaluation Board User Guide 6-9
Figure 6-8. Power Supply
D12 F1
1N914 1
U19 LT1507CS8-3.3 VSW 3
2 C55 22pF / 25V J1 SMT6T15CA Jack Dia.2.1mm C59 22pF / 25V 1 1 JP6 2 jumper_NO JP7 jumper_NO SHDN 1 2 SHDN_1 D18 10MQ100N D19 10MQ100N 1000m A/30V D14 D16 10MQ100N D17 10MQ100N C57B 10F / 25V C57 10F / 25V 4 5
VIN SHTDN SYNC
BOOST
C54 100nF
L1
VCC3V3
10H 7 JP5 jumper_NO D15 1N5817 C58B 2
SENSE GND VC
I Vddio
VDDPLL
SHDN_2
+
C58
+
6
8
R55 100K 5%
100F / 10V 100F / 10V C60 3,3nF / 10% VDDA
1
VDDIO
1
SHDN
SH1 shield
VDDCORE=3.3V
VDDIO JP8 jumper_3P 2 U20 VCC3V3 4 Vin Vout 1 VCC1V8 VDDCORE
I Vddcore
I Vddbu
R29 VSAVE=3V OR R30 not use R50 Radj 1 JP9 2 jumper_NO VDDBU
TP4 Test Point Corner 4
TP3 Test Point Corner 3
BT1 3V Button Pile
Vddbu=1V84 with R30=620k R29=330k Vddbu=3V with R29=0R and R30 off
GNDBU
RTC SAVE
GNDBU
GNDA
GNDPLL
Appendix B - Schematics
Title Size
EVALUATION BOARD FOR AT91M55200/800
Document Number Rev
A4
Date:
POWER SUPPLY / BATTERY
Monday, December 18, 2000
Sheet
5
7
of
8
U27 1 2 3
16
8
U29 1 2 3 NSPICS8 NSPICS[5..8] IOB_[68..71]
16
8
6-10
VCC3V3 U21 EBI_41 U23 R51 100k 1 2 A0 A1 WP 19 SI SO SCK CS NC NC NC 4 5 6 NC NC NC C65 100nF NSPICS1 13 CS SI SO SCK MOSI MISO SPCK 15 16 14 NSPICS0 13 4 5 6 15 16 14 MOSI MISO SPCK VCC 20 R34 100k R35 100k R31 100k EBI_41 NRST RDY/BUSY RESET WP NRST VCC RDY/BUSY RESET WP VCC R32 1 2 3 7 1 2 3 7 100k R33 VCC3V3 100k VCC3V3 U22 VCC3V3 VCC3V3 VCC3V3 VCC3V3 CB13 1 2 C67 100nF C66 100nF 3 4 5 6 7 8 9 NC NC NC NC NC NC NC NC NC NC NC NC NC 18 17 16 15 14 13 2 GND GND AT45DB321-TC 8 SDA1 SCL1 SDA SCL 10 AT24C512W1-10SC-2.7 11 12 9 10 11 12 NC NC NC NC NC NC NC NC AT45DB321-TC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC 9 10 11 12 GND 8 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC3V3 U25 R36 NRST R38 VCC3V3 VCC3V3 R40 100k 4 5 6 NC NC NC NC NC NC NC AT45DB321-TC 9 10 11 12 C89 100nF CS NSPICS2 13 MOSI MISO SPCK SI SO SCK 15 16 14 100k 1 2 3 RDY/BUSY RESET WP VCC 7 100k VCC3V3 R37 100k NRST R39 100k MOSI MISO SPCK C68 100nF NSPICS3 15 16 14 13 4 5 6 9 10 11 12 GND 8 1 2 3 VCC3V3 U26 RDY/BUSY RESET WP VCC 7 VCC3V3 SI SO SCK CS NC NC NC NC NC NC NC AT45DB321-TC VCC3V3 R52 100K U28 NSPICS4 MOSI MISO SPCK MOSI MISO SPCK 1 5 2 6 CS SI SO SCK VCC HOLD WP GND 8 7 3 4 AT25256W-10SC-2.7 VCC3V3 C70 100nF R53 100K C69 100nF
Appendix B - Schematics
SDA
CB14
Figure 6-9. SPI and I2C Memories
SCL
1
NPCS[0..3]
NPCS0 NPCS1 NPCS2
1 2 4 & EN
74LV138D VCC3V3
BIN/OCT
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC GND
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 8
NPCS3
VCC3V3
6 4 5
0 1 2 3 4 5 6 7
15 14 13 12 11 10 9 7 NSPICS0 NSPICS1 NSPICS2 NSPICS3 NSPICS4 NSPICS5 NSPICS6 NSPICS7
1 2 4 & EN
74LV138D C90 VCC3V3 100nF
BIN/OCT
6 4 5
0 1 2 3 4 5 6 7
15 14 13 12 11 10 9 7
Title Size Date:
EVALUATION BOARD FOR AT91M55200/800
Document Number Rev
A4 SERIAL MEMORIES
Monday, December 18, 2000
Sheet
5
8
of
AT91EB55 Evaluation Board User Guide
8
Section 7 Appendix C - Bill of Material
Table 1. Bill of Material
Item 1 2 3(1) Qty 1 2 3 Reference BT1 CB16 CB18 C1, C2, C3, C4, C5, C12, C13, C16, C17, C18, C19, C22, C28, C29, C30, C31, C32, C36, C38, C39, C42, C49, C50, C51, C52, C53, C54, C65, C66, C67, C68, C69, C70, C89, C90, C91, C94, C95, C96 C10, C11, C14, C15 C20, C21, C23, C24, C26, C27 C25, C71, C72, C73, C74, C75, C76, C77, C82, C83, C86 C33, C37, C40 C41, C63 C43, C47, C48 C44 C45 C46 C55, C59 C57 CB_NO Part 3V Button Pile Designation Li/MnO2 3V 180 mAH pile UL: MH13654(N) 3 position jumper (jumper between 2-3) If AT49BV1614-90TC is used, do not connect the jumper
4
41
100 nF
Ceramic X7R/10V
5 6
4 6
47 nF 22 pF
Ceramic X7R/10V Ceramic NPO/10V
7 8 9 10 11 12 13 14 15
11 3 2 3 1 1 1 2 1
10 nF 1 F/16V 10 F/16V 10 pF 4 - 25 pF 68 pF/10% 680 pF/10% 22 pF/25V 10 F/25V
Ceramic X7R/16V Tantalum 16V/10%/TAJ Tantalum 16V/10%/TAJ Ceramic NPO/10V/5% Adjustable Capacitor, serial TZBX4 Ceramic X7R/10V/10% Ceramic X7R/10V/10% Ceramic X7R/25V 25V ESR < 0.5/0.5Arms
AT91EB55 Evaluation Board User Guide
7-1
Appendix C - Bill of Material Table 1. Bill of Material (Continued)
Item 16 17 18 19 Qty 1 1 3 6 Reference C58 C60 C61, C62, C64 C78, C79, C80, C81, C84, C85 D1, D2, D3, D4, D5, D6, D7, D8, D10, D11 D9 D12 D14 D15 D16,D17,D18,D19 F1 JP1,JP8 JP5,JP7,JP9 J1 L1 P3 Part 100 F/10V 3.3 nF/10% 1 F/10% 10 pF Designation Tantalum 10V ESR < 0.5 Ceramic X7R/25V/10% Ceramic X7R/10V/10% Ceramic X7R/16V Red LED H.R. 3mm/ T1/ 7mcd 60 Diode signal Diode signal Transil 12.8V/600W/ VBRmini/14.3V Schottky diode 1A/0.45V Diode rectifying 0.62V/0.77A Fuse rarm. 1000 mA/30V 3 point jumper 2 point jumper Jack socket 2.1mm Self 10 H at 1A and 500 kHz Sub D 9b Female socket, right angle, mechanical strength, locking Sub D 9b Male socket, right angle, mechanical strength, locking HE10 2x10 socket, low profile, right angle
20 21 22 23 24 25 26 27 28 29 30 31
10 1 1 1 1 4 1 3 6 1 1 1
Red LED BAS32L 1N914 SMT6T15CA 1N5817 10MQ060N 1000 mA jumper_3P jumper_NO Jack Diameter 2.1mm 10 H Sub D 9b F
32
1
P4
Sub D 9b M
33
1
P5 R3, R4, R5, R14, R15, R16, R17, R25, R26, R27, R31, R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R51, R55 R56, R57 R6, R7, R8, R9, R10, R11, R12, R13, R23, R24 R18 R20 RR1, RR2, RR3, RR4 R29
HE10 2x10
34
27
100K
Resistor 5%
35 36 37 38 39 40
2 10 1 1 4 1
10K 100R 270K 287R 1% E48 100K 0R
Resistor 5% Resistor 5% Resistor 5% Resistor 1% Resistance network (4 resistors with 1 common point) Shunt OR
7-2
AT91EB55 Evaluation Board User Guide
Appendix C - Bill of Material Table 1. Bill of Material (Continued)
Item 41 Qty 16 Reference R22, R42, R43, R44, R45, R46, R48, R52, R53, R54 SW1, SW2, SW3, SW4 SW5 S1, S2 TP1, TP2, TP3, TP4 U1 U4, U5 U6 U8 U9 U10 U12 U13 U14, U15 U16 U30 U17, U18 U19 U20 U21 U23 U27, U29 U28 Y2 Y4 PS1, PS2, PS3, PS4 Part 100K Designation Resistor 5% Push button with black cabochon Push button with red cabochon CMS Push button CMS Test point Flash 2M bytes x 16-bits Static memory: 128k x 8-15 ns (double implantation) Reverser (LVC serial) Buffer Tri-state buffer Driver RS232 + ESD "E" Microcontroller Temperature sensor Reference of voltage 2V5 0.5% D flip flop (LVC serial) D Flip Flop (LCX serial) Circuit LVD-reset. (Threshold 2.7V; Timeout = 1 ms) Voltage Regulator DC/DC Voltage Regulator DC/DC Serial DataFlash (wired according to availability) EEPROM 64K bytes Decoder (3 to 8) EEPROM 32K bytes Crystal 32768 kHz, 20 ppm at 25C Crystal 16 MHz, 30ppm at 25c Plastic bases H > 10mm
42 43 44 45 46 47(2) 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 Notes:
4 1 2 4 1 1 1 1 1 1 1 1 2 1 1 2 1 1 4 1 2 1 1 1 4
TP 33 TP 33 Push Button Test Point Corner AT49BV1614-90TC IDT71V124SA15PH 74LVC04AD 74LV244D 74LV125D MAX3223ECAP AT91M55800A LM61BIM3 REF192GS 74LVC74AD 74LCX74 MAX6315US27D1T LT 1507CS8-3.3 LTC 1503CS8-2 AT45DB321-TC AT24C512W110SC-2.7 74LV138D AT25256W-10SC2.7 Crystal 32768 kHz Crystal 16 MHz Board Support
1. If the AT49BV1614 is replaced with the AT49BV1604, the jumper must be connected. 2. The EB55 is equipped with SRAM U2/U3 or U4/U5 (the difference lies in case type only). The choice is made according to availability.
AT91EB55 Evaluation Board User Guide
7-3
Appendix C - Bill of Material
7-4
AT91EB55 Evaluation Board User Guide
Section 8 Appendix D - Flash Memory
The following figure shows the embedded software mapping after the remap. It describes the location for the different programs in the AT49BV16X4 flash memory and the division into sectors. Figure 1. EB55 Flash Memory Software Location
0x011FFFFF
Not Used 16 Sectors (64K byte/sector) 1MB User Mode
Led Swing Application (example) 0x01100000
Not Used
15 Sectors (64K Byte/sector) 1MB Standard Mode
0x01010000 6 Sectors (8K Byte/sector)
Angel Software 0x01004000
0x01000000
Functional Test Software, 2 Sectors SRAM Downloader, Boot (8K Byte/sector)
AT91EB55 Evaluation Board User Guide
8-1
Appendix D - Flash Memory
AT91EB55 Evaluation Board User Guide
8-2
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(c) Atmel Corporation 2001. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life suppor t devices or systems. ARM7TDMI, Angel and AMBA are trademarks of ARM Limited. DataFlash is a trademark of Atmel Corporation. Terms and product names in this document may be trademarks of others. Printed on recycled paper.
1709A-06/01/0M

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